Towards An Efficient Low Frequency Energy Recovery Dynamic Logic

A large number of energy recovery circuits have been described to reduce the power consumption of CMOS logic circuits. Many of these circuits use diode connected transistors, accurately timed multiple clocks and self resonating power clocks. Boost logic is a 2 phase high speed energy recovery family that voltage scaling and high gate overdrive to achieve highly efficient energy recovery. In this report, we investigate 3 new designs to improve the energy recovery efficiency of Boost logic at low frequencies. The first design involves the use of CMOS stacks in the evaluation stage of Boost logic. Simulations show a significant reduction in crowbar current and hence energy dissipation, at the cost of high area overhead. The second design uses CMOS stacks and an inverter to create differential outputs in evaluation. Simulations indicate lesser energy dissipation but a lower operational range of frequencies because of sub-threshold operation of the inverter. Next we investigate a new design based on an energy recovery domino logic topology which achieves significant reduction in energy dissipation with small area overhead. We discuss the experimental results of HSPICE simulations with a 32-bit adder using the proposed circuit topologies. The logic proposed achieves energy saving of 65% to 25% in frequency range 20MHz to 150MHz over Boost logic. Simulations indicate that it is more robust to power supply variations compared to conventional CMOS.